/*
 * Copyright (c) 2009, artur
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the name of the author nor the names of any co-contributors
 *    may be used to endorse or promote products derived from this software
 *    without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 * SUCH DAMAGE.
 */

/*
 * /kiddie/include/arm/mach-integrator/platform.h
 * created: Jun 9, 2009
 *
 * TODO
 */


#ifndef _INTEGRATOR_PLATFORM_H_
#define _INTEGRATOR_PLATFORM_H_

#define INTEGRATOR_RAM_BASE			0x80000000
#define INTEGRATOR_RAM_SIZE			0x10000000	/*	Maximum size of RAM = 256M */
#define INTEGRATOR_HDR_BASE			0x10000000	/*	Card header base */

#define INTEGRATOR_CT_BASE			0x13000000	/*  Counter/Timers */
#define INTEGRATOR_IC_BASE			0x14000000	/*  Interrupt Controller */
#define INTEGRATOR_RTC_BASE			0x15000000	/*  Real Time Clock */
#define INTEGRATOR_UART0_BASE		0x16000000	/*  UART 0 */
#define INTEGRATOR_UART1_BASE		0x17000000	/*  UART 1 */
#define INTEGRATOR_KBD_BASE			0x18000000	/*  Keyboard */
#define INTEGRATOR_MOUSE_BASE		0x19000000	/*  Mouse */

/*
 * Mappings to common definitions
 */
#define HDR_BASE			INTEGRATOR_HDR_BASE
#define CT_BASE			INTEGRATOR_CT_BASE		/*  Counter/Timers */
#define PIC_BASE			INTEGRATOR_IC_BASE		/*  Primary Interrupt Controller */
#define RTC_BASE			INTEGRATOR_RTC_BASE		/*  Real Time Clock */
#define UART0_BASE		INTEGRATOR_UART0_BASE	/*  UART 0 */
#define UART1_BASE		INTEGRATOR_UART1_BASE	/*  UART 1 */
#define KBD_BASE			INTEGRATOR_KBD_BASE		/*  Keyboard */
#define MOUSE_BASE		INTEGRATOR_MOUSE_BASE	/*  Mouse */

/*
 * This area of memory contains a copy of the SPD data from the SPD EEPROM on the DIMM.
 * SPD Format:
 * | ByteNum |	Description |
 *   2			Memory type
 *   3 			Number of row address lines
 *   4 			Number of column address lines
 *   5  		Number of chip-select banks
 *   31 		Module bank density (MB divided by 4)
 *   18 		CAS latencies supported
 *   63 		Checksum
 *   64:71 		Manufacturer
 *   73:90 		Module part number
 *
 * Check for valid SPD data as follows:
 *    1. Add together all bytes 0 to 62.
 *    2. Logically AND the result with 0xFF.
 *    3. Compare the result with byte 63.
 * If the two values match, then the SPD data is valid
 *
 */
#define SPD_BASE_R				HDR_BASE + 0x100	/* Base addres of SPD */

#define CORE_ID_R				HDR_BASE
#define CORE_STATUS_R			HDR_BASE + 0x10		/* Core module status register  */
#define CORE_CTRL_R				HDR_BASE + 0x0C		/* Control register */
#define CORE_LOCK_R				HDR_BASE + 0x14
#define CORE_LMBUSCNT_R			HDR_BASE + 0x18		/* Core module local memory bus cycle counter */
#define CORE_AUXOSC_R			HDR_BASE + 0x1C		/* Auxiliary oscillator register */
#define CORE_SDRAM_STATUS_R		HDR_BASE + 0x20		/* Local SDRAM Status/Control register */
#define CORE_INIT_R				HDR_BASE + 0x24		/* Initialization register */
#define CORE_REFCNT_R			HDR_BASE + 0x28		/* reference clock cycle counter. Can be used as a real-time counter */


/*
 * Primary interrupt controller register address offsets.
 * The base physical address is mapped to PIC_BASE.
 */
#define PIC_IRQ_STATUS_R		0x00		/*	Read 22 IRQ gated interrupt status */
#define PIC_IRQ_RAWSTAT_R	0x04		/*	Read 22 IRQ raw interrupt status */
#define PIC_IRQ_ENABLESET_R	0x08		/*	Read/write 22 IRQ enable set */
#define PIC_IRQ_ENABLECLR_R	0x0C		/*	Write 22 IRQ enable clear */
#define PIC_INT_SOFTSET_R	0x10		/*	Read/write 16 Software interrupt set */
#define PIC_INT_SOFTCLR_R	0x14		/*	Write 16 Software interrupt clear */
#define PIC_FIQ_STATUS_R		0x20		/*	Read 22 FIQ gated interrupt status */
#define PIC_FIQ_RAWSTAT_R	0x24		/*	Read 22 FIQ raw interrupt status */
#define PIC_FIQ_ENABLESET_R	0x28		/*	Read/write 22 FIQ enable set */
#define PIC_FIQ_ENABLECLR_R	0x2C		/*	Write-only 22 FIQ enable clear */

/*
 *
 */
/* [31:29] - Reserved*/
#define PIC_BITS_TS_PENINT	0x10000000		/*	Touchscreen pen-down event interrupt [28] */
#define PIC_BITS_ETH_INT		0x08000000		/*	Ethernet interface interrupt [27] */
#define PIC_BITS_CPPLDINT	0x04000000		/*	Interrupt from secondary interrupt controller [26] */
#define PIC_BITS_AACIINT		0x02000000		/*	Audio interface interrupt [25] */
#define PIC_BITS_MMCIINT1	0x01000000		/*	MultiMedia card interface [24] */
#define PIC_BITS_MMCIINT0	0x00800000		/*	MultiMedia card interface [23] */
#define PIC_BITS_CLCDCINT	0x00400000		/*	Display controller interrupt [22] */
/* [21:11] - Reserved*/
#define PIC_BITS_LM_LLINT1	0x00000400		/*	Logic module low-latency interrupt 1 [10] */
#define PIC_BITS_LM_LLINT0	0x00000200		/*	Logic module low-latency interrupt 0 [9] */
#define PIC_BITS_RTCINT		0x00000100		/*	Real time clock interrupt [8] */
#define PIC_BITS_TIMERINT2	0x00000080		/*	Counter-timer 2 interrupt [7] */
#define PIC_BITS_TIMERINT1	0x00000040		/*	Counter-timer 1 interrupt [6] */
#define PIC_BITS_TIMERINT0	0x00000020		/*	Counter-timer 0 interrupt [5] */
#define PIC_BITS_MOUSEINT	0x00000010		/*	Mouse interrupt [4] */
#define PIC_BITS_KBDINT		0x00000008		/*	Keyboard interrupt [3] */
#define PIC_BITS_UARTINT1	0x00000004		/*	UART 1 interrupt [2] */
#define PIC_BITS_UARTINT0	0x00000001		/*	UART 0 interrupt [1] */
#define PIC_BITS_SOFTINT		0x00000000		/*	Software interrupt [0] */

/*
 * The UART registers. For more detailed information, refer to the
 * ARM PrimeCell UART (PL011) Technical Reference Manual. The base addresses for
 * the UARTs are:
 * 	0x16000000 UART0, the top port on the connector, also called serial A.
 * 	0x17000000 UART1, the bottom port on the connector, also called serial B.
 */
#define UART_DR_OFFST	0x00
#define UART_RS_OFFST	0x04
#define UART_CL_OFFST	0x04
#define UART_FR_OFFST	0x18	/* Flag register */
#define UART_BDR_OFFST	0x24	/* Baud rate divisor register */
#define UART_FDR_OFFST	0x28	/* Fractional baud rate divisor register */
#define UART_LCTRL_HIGH_OFFST	0x2C 	/* Line control high byte register */
#define UART_CTRL_OFFST	0x30	/* Control register */
#define UART_IFLS_OFFST	0x34	/* FIFO level */
#define UART_IMSC_OFFST	0x38	/* Interrupt mask register */
#define UART_ICR_OFFST	0x44	/* Interrupt clear register */

#define UART_TX_BUSY		0x8
#define UART_TX_FULL		0x20

/*
 * Clock/Timer registers
 */
#define TIMER1_VALUE_R		CT_BASE+0x100	/* Counter load value */
#define TIMER1_CURRENT_R		CT_BASE+0x104	/* Counter current value */
#define TIMER1_CTRL_R		CT_BASE+0x108	/* Control register */
#define TIMER1_CLEAR_R		CT_BASE+0x10C	/* Clear interrupt register */
#define TIMER1_RIS_R			CT_BASE+0x110	/* RAW interrupt status */
#define TIMER1_MIS_R			CT_BASE+0x114	/* Masked interrupt status */

/* TODO Move this into config.h */
#ifndef CONFIG_MMU
#warning "MMU TURNED OFF!!!!!!!!!!!"
#endif
#define MACH_RAM_BASE		INTEGRATOR_RAM_BASE
#define MACH_RAM_SIZE		INTEGRATOR_RAM_SIZE

#endif /* PLATFORM_H_ */
